1. Field of the invention
The present invention relates, in general, to the testing of integrated circuits and, more specifically, to a method of performing signature analysis in presence of corrupt bits.
2. Description of Related Art
In integrated circuits which are designed for embedded test, memory elements in the circuit are organized into a plurality of scan chains having respective serial inputs and serial outputs. The serial outputs are connected to a signature register through a masking circuit. The memory elements are connected to combinational logic circuits. During a scan test of the circuit, test patterns are serially loaded into the memory elements through the serial inputs and then applied to the circuit. The response of the combinational circuits is then captured by the memory elements and unloaded by shifting out the contents of the memory elements and applying it to the input of a signature register. Usually, the circuits are designed so that the response of the combinational circuits is predictable and repeatable. That is, the memory elements always capture the same output response to a given test pattern and the signature register always generates the same signature. However, there are circumstances in which it is desired to be able to compute a signature, even though the output response of the circuit is not completely predictable and repeatable. This is to allow the part of the output response that is predictable and repeatable to be analyzed. A non-repeatable output response can result from logic being tested using some test patterns that are not valid functional patterns. It could also be the result of a design error or a defect. Whatever the reason may be, the corrupt bits (each memory element stores one bit of the output response) must be masked so that the signature register can generate a repeatable signature for a xe2x80x98good circuitxe2x80x99, i.e. a circuit that is good except for some of the logic generating the corrupt bits.
Several methods have been developed for masking corrupt bits during signature computation. WO 01/38889 and U.S. Pat. Nos. 5,694,402, 4,817,093 and 6,158,033 are representative examples. U.S. Pat. No. 6,158,033 is not applicable to scannable circuits and is not discussed any further herein. The three other methods propose several embodiments to perform diagnosis of scannable circuits. None of the embodiments or combinations thereof have the features discussed above because these features are not required to perform diagnosis. In fact, the fault coverage of each test is minimized to isolate the source of the corrupt bits. Several such tests must be applied, resulting in long test times. For embodiments that require masking of individual bit positions in the scan chain, it is well known that testers are not able to provide mask data at high clock rates. Also, no mechanism has thusfar been proposed for providing default mask data information on-chip so that a test can be executed autonomously in the field.
For all these reasons, there is a need for an efficient signature analysis method for use in performing high quality, at-speed tests in presence of corrupt bits.
The present invention seeks to provide a masking method and circuit which will maximize the fault coverage of the test, minimize the amount of additional logic required to implement the mask circuitry, minimize the number of clock cycles required to run the test; maximize the clock rate at which the signature can be computed; minimize the amount of information to be stored on the tester; and provide a default mode that does not require any information from the tester. These features will allow an at-speed production test or field test to be performed while maximizing fault coverage.
One aspect of the present invention is generally defined as A method of masking corrupt bits in test response pattern scan chains in an integrated circuit, comprising loading and applying a set of test patterns in the scan chains so as to obtain corresponding test response patterns; and masking bits of the test response patterns located in scan chains identified by a chain mask and at a position identified by a position mask.
One embodiment of the present invention provides individual registers for a position mask and a chain mask and the method further comprises loading a position mask into a position mask register with the position mask identifying scan chain bit positions having corrupt bits; and loading a chain mask into a chain mask register, with the chain mask identifying scan chains having corrupt bits.
Another embodiment provides for loading a position mask and a chain mask into the same register. The testing method comprises loading and applying the two masks in a sequence which comprises loading one of a position mask and a chain mask into a mask register; loading and applying first test patterns to the circuit so as to obtain first circuit test response patterns; while scanning out the first test response patterns along the scan chains, applying a masking bit in the first test response patterns according to the one mask in the mask register; loading and applying second test patterns to the circuit so as to obtain a second circuit test response; loading the other of the position mask and chain mask into the mask register; while scanning out the second test response patterns along the scan chains, applying a masking bit according to the other mask in the mask register.
Another aspect of the present invention is generally defined as a masking circuit for use in an integrated circuit for masking bits in scan chains, comprising mask storage means for storing a bit position mask identifying scan chain bit positions to be masked and a chain mask identifying scan chains having bits to be masked; and gating means associated with each scan chain, each gating means having a scan chain input for receiving the serial output of an associated scan chain, a position mask input connected to a position mask output of the storage means, and a chain mask inputs connected to chain mask outputs of the storage means, and a gating means output corresponding to each scan chain, the gating means being operable to gate a masking bit derived from the position and chain mask inputs with the scan chain serial output and apply a resulting gated bit to the gating means output.